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STM32F103x6 STM32F103x8 STM32F103xB
Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces
Preliminary Data
Features
Core: ARM 32-bit CortexTM-M3 CPU - 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz - Single-cycle multiplication and hardware division - Nested interrupt controller with 43 maskable interrupt channels - Interrupt processing (down to 6 CPU cycles) with tail chaining
LQFP48 7 x 7 mm LQFP100 14 x 14 mm LQFP64 10 x 10 mm BGA100 10 x 10 mm
Debug mode - Serial wire debug (SWD) & JTAG interfaces Up to 80 fast I/O ports - 32/49/80 5 V-tolerant I/Os - All mappable on 16 external interrupt vectors - Atomic read/modify/write operations
Memories - 32-to-128 Kbytes of Flash memory - 6-to-20 Kbytes of SRAM
Clock, reset and supply management - 2.0 to 3.6 V application supply and I/Os - POR, PDR, and programmable voltage detector (PVD) - 4-to-16 MHz quartz oscillator - Internal 8 MHz factory-trimmed RC - Internal 32 kHz RC - PLL for CPU clock - Dedicated 32 kHz oscillator for RTC with calibration
Up to 7 timers - Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter - 16-bit, 6-channel advanced control timer: up to 6 channels for PWM output Dead time generation and emergency stop - 2 x 16-bit watchdog timers (Independent and Window) - SysTick timer: a 24-bit downcounter
Low power - Sleep, Stop and Standby modes - VBAT supply for RTC and backup registers
Up to 9 communication interfaces - Up to 2 x I2C interfaces (SMBus/PMBus) - Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) - Up to 2 SPIs (18 Mbit/s) - CAN interface (2.0B Active) - USB 2.0 full speed interface
2 x 12-bit, 1 s A/D converters (16-channel) - - - - Conversion range: 0 to 3.6 V Dual-sample and hold capability Synchronizable with advanced control timer Temperature sensor
DMA - 7-channel DMA controller - Peripherals supported: timers, ADC, SPIs, I2Cs and USARTs
Table 1.
Reference
Device summary
Root part number STM32F103C8, STM32F103R8 STM32F103V8
STM32F103x6 STM32F103C6, STM32F103R6 STM32F103x8
STM32F103xB STM32F103RB STM32F103VB
July 2007
Rev 2
1/67
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STM32F103xx
Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 4 5
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 5.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 27 Embedded reset and power control block characteristics . . . . . . . . . . . 28 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 42 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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STM32F103xx 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18
Contents TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 54 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.1 Future family enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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List of tables
STM32F103xx
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device features and peripheral counts (STM32F103xx performance line). . . . . . . . . . . . . . 7 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 28 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Maximum current consumption in Run and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . 29 Maximum current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . 30 Typical current consumption in Run and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Typical current consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . 32 High-speed external (HSE) user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 USB: Full speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ADC accuracy (fPCLK2 = 14 MHz, fADC = 14 MHz, RAIN <10 k, VDDA = 3.3 V). . . . . . . . . 55 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . . 59 LQFP100 - 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 61 LQFP64 - 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 62 LQFP48 - 48 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 63 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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STM32F103xx
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 STM32F103xx performance line BGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Typical application with a 8-MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Unused I/O pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SPI timing diagram - slave mode and CPHA = 11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 57 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 57 LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . 59 Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 60 LQFP100 - 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . 61 LQFP64 - 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 LQFP48 - 48 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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Introduction
STM32F103xx
1
Introduction
This datasheet provides the STM32F103xx performance line ordering information and mechanical device characteristics. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming reference manual, pm0042, available from www.st.com. For information on the Cortex-M3 core please refer to the Cortex-M3 Technical Reference Manual.
2
Description
The STM32F103xx performance line family incorporates the high-performance ARM Cortex-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 128Kbytes and SRAM up to 20 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs, an USB and a CAN. The STM32F103xx performance line family operates in the - to +105 C temperature 40 range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows to design low-power applications. The complete STM32F103xx performance line family includes devices in 4 different package types: from 48 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx performance line microcontroller family suitable for a wide range of applications:

Motor drive and application control Medical and handheld equipment PC peripherals gaming and GPS platforms Industrial applications: PLC, inverters, printers, and scanners Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
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STM32F103xx
Description
2.1
Device overview
Table 2. Device features and peripheral counts (STM32F103xx performance line) Peripheral
Flash - Kbytes SRAM - Kbytes Timers General purpose Advanced Control SPI I2C USART USB CAN GPIOs 12-bit synchronized ADC Number of channels CPU frequency Operating voltage Operating temperature Packages LQFP48 1 1 2 1 1 32 2 10 channels 72 MHz 2.0 to 3.6 V -40 to +85 C / -40 to +105 C LQFP64 LQFP100, BGA100 STM32F103Cx 32 10 2 1 2 2 3 1 1 1 1 2 1 1 49 2 16 channels 64 20 3 32 10 2 1 2 2 3 1 1 STM32F103Rx 64 20 3 128 STM32F103Vx 64 20 3 1 2 2 3 1 1 80 128
Communication
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Description
STM32F103xx
2.2
Overview
ARM(R) CortexTM-M3 core with embedded Flash and SRAM
The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F103xx performance line family having an embedded ARM core, is therefore compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family.
Embedded Flash memory
Up to 128 Kbytes of embedded Flash is available for storing programs and data.
Embedded SRAM
Up to 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
Nested vectored interrupt controller (NVIC)
The STM32F103xx performance line embeds a Nested Vectored Interrupt Controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of CortexM3) and 16 priority levels.

Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detectors lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect external line with pulse width lower than the Internal APB2 clock period. Up to 80 GPIOs are connected to the 16 external interrupt lines.
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STM32F103xx
Description
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected and is monitored for failure. During such a scenario, it is disabled and software interrupt management follows. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow the configuration of the AHB frequency, the High Speed APB (APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and the High Speed APB domains is 72 MHz. The maximum allowed frequency of the Low Speed APB domain is 36 MHz.
Boot modes
At startup, boot pins are used to select one of three boot options:

Boot from User Flash Boot from System Memory Boot from SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by using the USART.
Power supply schemes

VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL. In VDD range (ADC is limited at 2.4 V). VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
Power supply supervisor
The device has an integrated Power On Reset (POR)/Power Down Reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 9: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD.
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Description
STM32F103xx
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.

MR is used in the nominal regulation mode (Run) LPR is used in the Stop modes. Power down is used in Standby Mode: the regulator output is in high impedance: the kernel circuitry is powered-down, inducing zero consumption (but the contents of the registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby Mode, providing high impedance output.
Low-power modes
The STM32F103xx performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources:
Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
Stop mode Stop mode allows to achieve the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup.
Standby mode The Standby mode allows to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI and the HSE RC oscillators are also switched off. After entering Standby mode, SRAM and registers content are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose and advanced control timers TIMx and ADC.
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STM32F103xx
Description
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers (ten 16-bit registers) can be used to store data when VDD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by an external 32.768 kHz oscillator, the internal low power RC oscillator or the High Speed External clock divided by 128. The internal low power RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application time out management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It features:

A 24-bit down counter Autoreload capability Maskable system interrupt generation when the counter reaches 0. Programmable clock source
General purpose timers (TIMx)
There are up to 3 synchronizable standard timers embedded in the STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one pulse mode output. This gives up to 12 input captures / output compares / PWMs on the largest packages. They can work together with the Advanced Control Timer via the Timer Link feature for synchronization or event chaining. The counter can be frozen in debug mode. Any of the standard timers can be used to generate PWM outputs. Each of the timers has independent DMA request generations.
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Description
STM32F103xx
Advanced control timer (TIM1)
The advanced control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for

Input Capture Output Compare PWM generation (edge or center-aligned modes) One Pulse Mode output Complementary PWM outputs with programmable inserted dead-times.
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). The counter can be frozen in debug mode. Many features are shared with those of the standard TIM timers which have the same architecture. The advanced control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining.
IC bus
Up to two IC bus interfaces can operate in multi-master and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus.
Universal synchronous/asynchronous receiver transmitter (USART)
One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816 compliant and have LIN Master/Slave capability. All USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 8-bit to 16-bit. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller.
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.
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STM32F103xx
Description
Universal serial bus (USB)
The STM32F103xx performance line embeds a USB device peripheral compatible with the USB Full-speed 12 Mbs. The USB interface implements a full speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock source is generated from the internal main PLL.
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed
ADC (analog to digital converter)
Two 12-bit Analog to Digital Converters are embedded into STM32F103xx performance line devices and each ADC shares up to 16 external channels, performing conversions in singleshot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow:

Simultaneous sample and hold Interleaved sample and hold Single shunt
The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the standard timers (TIMx) and the Advanced Control timer (TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers.
Temperature sensor
The temperature sensor has to generate a linear voltage with any variation in temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value.
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
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Description Figure 1. STM32F103xx performance line block diagram
JTAG & SWD JNTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF pbus Ibus Trace Controller flash obl Interface POWER VOLT. REG. 3.3V TO 1.8V @VDD
STM32F103xx
VDD = 2 to 3.6V
VSS
CORTEX M3 CPU
Fmax: 72 MHz Dbus
FLASH 128 KB 64 bit
BusMatrix
NVIC
System
SRAM 20 KB
PCLK1 PCLK2 HCLK FCLK RC 8 MHz RC 32 kHz @VDDA @VBAT AHB2 APB1 PLL & CLOCK MANAGT
@VDD XTAL OSC 4-16 MHz OSC_IN OSC_OUT
GP DMA
AHB:Fmax=48/72 MHz 7 channels
IWDG Standby interface VBAT OSC32_IN OSC32_OUT ANTI_TAMP
@VDDA NRST VDDA VSSA SUPPLY SUPERVISION POR / PDR PVD 80AF PA[15:0] PB[15:0] PC[15:0] PD[15:0] PE[15:0] EXTI WAKEUP GPIOA GPIOB GPIOC GPIOD GPIOE APB2 : Fmax=48 / 72 MHz Rst Int
AHB2 APB2
XTAL 32 kHz RTC AWU Backup reg
Backup interface TIM2 TIM3 APB1 : Fmax=24 / 36 MHz TIM 4 USART2 USART3 SPI2 2x(8x16bit) I2C1 I2C2 bxCAN USB 2.0 FS 4 Channels 4 Channels 8 Channels RX,TX, CTS, RTS, SmartCard as AF RX,TX, CTS, RTS, SmartCard as AF MOSI,MISO,SCK,NSS as AF SCL,SDA,SMBAL as AF SCL,SDA as AF USBDP/CANTX USBDM/CANRX
4 Channels 3 compl. Channels Brk input MOSI,MISO, SCK,NSS as AF RX,TX, CTS, RTS, SmartCard as AF
TIM1 SPI1 USART1 @VDDA
16AF VREF+ VREF-
12bit ADC1 IF 12bit ADC2 IF SRAM 512B WWDG Temp sensor
ai14390
1. TA = -40 C to +105 C (junction temperature up to 125 C). 2. AF = alternate function on I/O port pin.
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STM32F103xx
Pin descriptions
3
Pin descriptions
Figure 2. STM32F103xx performance line LQFP100 pinout
VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 PE3 PE4 PE5 PE6 VBAT PC13-ANTI_TAMP PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LQFP100
VDD_2 VSS_2 NC PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
ai14391
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Pin descriptions Figure 3. STM32F103xx performance line LQFP64 pinout
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14
STM32F103xx
VBAT PC13-ANTI_TAMP PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12
PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
ai14392
Figure 4.
STM32F103xx performance line LQFP48 pinout
VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14
VBAT PC13-ANTI_TAMP PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2
48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12
PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1
ai14393
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STM32F103xx Figure 5.
1
Pin descriptions
STM32F103xx performance line BGA100 ballout
2 3 4 5 6 7 8 9 10
A
PC14PC13OSC32_IN ANTI_TAMP
PE2
PB9
PB7
PB4
PB3
PA15
PA14
APA13
B
PC15OSC32_OUT
VBAT
PE3
PB8
PB6
PD5
PD2
PC11
PC10
PA12
C
OSC_IN
VSS_5
PE4
PE1
PB5
PD6
PD3
PC12
PA9
PA11
D
OSC_OUT
VDD_5
PE5
PE0
BOOT0
PD7
PD4
PD0
PA8
PA10
E
NRST
PCD
PE6
VSS_4
VSS_3
VSS_2
VSS_1
PD1
PC9
PC7
F
PC0
PC1
PC3
VDD_4
VDD_3
VDD_2
VDD_1
NC
PC8
PC6
G
VSSA
PA0-WKUP
PA4
PC4
PB2
PE10
PE14
PB15
PD11
PD15
H
VREF-
PA1
PA5
PC5
PE7
PE11
PE15
PB14
PD10
PD14
J
VREF+
PA2
PA6
PB0
PE8
PE12
PB10
PB13
PD9
PD13
K
VDDA
PA3
PA7
PB1
PE9
PE13
PB11
PB12
PD8
PD12
AI16001
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Pin descriptions Table 3.
Pins Type(1) LQFP100 BGA100 LQFP48 LQFP64 Pin name
STM32F103xx
Pin definitions
I / O Level(2) Main function(3) (after reset)
Default alternate functions
A3 B3 C3 D3 E3 B2 A2 A1 B1 C2 D2 C1 D1 E1 F1 F2 E2 F3 G1 H1 J1 K1 G2
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
PE2/TRACECK PE3/TRACED0 PE4/TRACED1 PE5/TRACED2 PE6/TRACED3 VBAT PC13-ANTI_TAMP(4) PC14-OSC32_IN(4) PC15-OSC32_OUT(4) VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0/ADC_IN10 PC1/ADC_IN11 PC2/ADC_IN12 PC3/ADC_IN13 VSSA VREFVREF+ VDDA PA0-WKUP/ USART2_CTS/ ADC_IN0/TIM2_CH1_ETR PA1/USART2_RTS/ ADC_IN1/TIM2_CH2 PA2/USART2_TX/ ADC_IN2/ TIM2_CH3 PA3/USART2_RX/ ADC_IN3/TIM2_CH4 VSS_4 VDD_4
I/O I/O I/O I/O I/O S I/O I/O I/O S S I O I/O I/O I/O I/O I/O S S S S I/O
FT FT FT FT FT
PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0
TRACECK TRACED0 TRACED1 TRACED2 TRACED3
ANTI_TAMP
ADC_IN10 ADC_IN11 ADC_IN12 ADC_IN13
WKUP/USART2_CTS(6)/AD C_IN0/ TIM2_CH1_ETR(6) USART2_RTS(6)/ ADC_IN1/ TIM2_CH2(6) USART2_TX(6)/ ADC_IN2/ TIM2_CH3(6) USART2_RX(6)/ ADC_IN3/TIM2_CH4(6)
H2
11
15
24
I/O
PA1
J2 K2 E4 F4
12 13 -
16 17 18 19
25 26 27 28
I/O I/O S S
PA2 PA3 VSS_4 VDD_4
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STM32F103xx Table 3.
Pins Type(1) LQFP100 BGA100 LQFP48 LQFP64 Pin name
Pin descriptions
Pin definitions (continued)
I / O Level(2) Main function(3) (after reset)
Default alternate functions
G3 H3 J3 K3 G4 H4 J4 K4 G5 H5 J5 K5 G6 H6 J6 K6 G7 H7 J7 K7 E7 F7
14 15 16 17 18 19 20 21 22 23 24
20 21 22 23 24 25 26 27 28 29 30 31 32
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PA4/SPI1_NSS/ USART2_CK/ADC_IN4 PA5/SPI1_SCK/ ADC_IN5 PA6/SPI1_MISO/ ADC_IN6/TIM3_CH1 PA7/SPI1_MOSI/ ADC_IN7/TIM3_CH2 PC4/ADC_IN14 PC5/ADC_IN15 PB0/ADC_IN8/ TIM3_CH3 PB1/ADC_IN9/ TIM3_CH4 PB2 / BOOT1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10/I2C2_SCL/ USART3_TX PB11/I2C2_SDA / USART3_RX VSS_1 VDD_1
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S FT FT FT FT FT FT FT FT FT FT FT FT
PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2/BOOT1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1
SPI1_NSS(6)/ USART2_CK(6)/ ADC_IN4 SPI1_SCK(6)/ ADC_IN5 SPI1_MISO(6)/ ADC_IN6/TIM3_CH1(6) SPI1_MOSI(6)/ ADC_IN7/TIM3_CH2(6) ADC_IN14 ADC_IN15 ADC_IN8/TIM3_CH3(6) ADC_IN9/TIM3_CH4(6)
I2C2_SCL/USART3_TX(5)(6) I2C2_SDA/ USART3_RX(5)(6)
K8
25
33
PB12/SPI2_NSS / 51 I2C2_SMBAl/ USART3_CK / I/O TIM1_BKIN PB13/SPI2_SCK / USART3_CTS / TIM1_CH1N PB14/SPI2_MISO / USART3_RTS / TIM1_CH2N
FT
PB12
SPI2_NSS(5) /I2C2_SMBAl(5)/ USART3_CK(5)(6)/ TIM1_BKIN(6) SPI2_SCK(5)/ USART3_CTS(5)(6)/ TIM1_CH1N (6) SPI2_MISO(5) /USART3_RTS(5)(6) TIM1_CH2N (6)
J8
26
34
52
I/O
FT
PB13
H8
27
35
53
I/O
FT
PB14
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Pin descriptions Table 3.
Pins Type(1) LQFP100 BGA100 LQFP48 LQFP64 Pin name
STM32F103xx
Pin definitions (continued)
I / O Level(2) Main function(3) (after reset)
Default alternate functions
G8 K9 J9 H9 G9 K10 J10 H10 G10 F10 E10 F9 E9 D9 C9
28 -
36 37 38 39
54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
PB15/SPI2_MOSI TIM1_CH3N PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8/USART1_CK/ TIM1_CH1/MCO PA9/USART1_TX/ TIM1_CH2 PA10/USART1_RX/ TIM1_CH3 PA11 / USART1_CTS/ CANRX / USBDM/ TIM1_CH4 PA12 / USART1_RTS/ CANTX / USBDP/ TIM1_ETR PA13/JTMS/SWDIO
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT FT
PB15 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PC6 PC7 PC8 PC9 PA8 PA9 PA10
SPI2_MOSI(5)/ TIM1_CH3N(6)
29 30
40 41 42 43
USART1_CK/ TIM1_CH1(6)/MCO USART1_TX(6)/ TIM1_CH2(6) USART1_RX(6)/ TIM1_CH3(6) USART1_CTS/ CANRX(6)/ TIM1_CH4(6) / USBDM USART1_RTS/ CANTX(6) / TIM1_ETR(6) / USBDP PA13
D10 31
C10 32
44
70
I/O
FT
PA11
B10 33 A10 34 F8 E6 F6 A9 A8 B9 B8 C8 35 36 37 38 -
45 46 47 48 49 50 51 52 53
71 72 73 74 75 76 77 78 79 80
I/O I/O
FT FT
PA12 JTMS/SWDIO
Not connected VSS_2 VDD_2 PA14/JTCK/SWCLK PA15/JTDI PC10 PC11 PC12 S S I/O I/O I/O I/O I/O FT FT FT FT FT VSS_2 VDD_2 JTCK/SWCLK JTDI PC10 PC11 PC12 PA14 PA15
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STM32F103xx Table 3.
Pins Type(1) LQFP100 BGA100 LQFP48 LQFP64 Pin name
Pin descriptions
Pin definitions (continued)
I / O Level(2) Main function(3) (after reset)
Default alternate functions
D8 E8 B7 C7 D7 B6 C6 D6 A7 A6 C5 B5 A5 D5 B4 A4 D4 C4 E5 F5
5 6
5 6 54
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
PD0 PD1 PD2/TIM3_ETR PD3 PD4 PD5 PD6 PD7 PB3/JTDO/TRACESWO PB4/JNTRST PB5/I2C1_SMBAl PB6/I2C1_SCL/ TIM4_CH1 PB7/I2C1_SDA/ TIM4_CH2 BOOT0 PB8/TIM4_CH3 PB9/TIM4_CH4 PE0/TIM4_ETR PE1 VSS_3 VDD_3
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O S S
FT FT FT FT FT FT FT FT FT FT
OSC_IN(7) OSC_OUT(7) PD2 PD3 PD4 PD5 PD6 PD7 JTDO JNTRST PB5 PB3/TRACESWO PB4 I2C1_SMBAl I2C1_SCL(6)/ TIM4_CH1(5)(6) I2C1_SDA(6)/ TIM4_CH2(5) (6) TIM3_ETR
39 40 41 42 43 44 45 46 47 48
55 56 57 58 59 60 61 62 63 64
FT FT
PB6 PB7 BOOT0
FT FT FT FT
PB8 PB9 PE0 PE1 VSS_3 VDD_3
TIM4_CH3(5) (6) TIM4_CH4(5) (6) TIM4_ETR(5)
1. I = input, O = output, S = supply, HiZ = high impedance. 2. FT= 5 V tolerant. 3. Function availability depends on the chosen device. Refer to Table 2 on page 7. 4. PC13, PC14 and PC15 are supplied through the power switch, and so their use in ouptut mode is limited: they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time. 5. Available only on devices with a Flash memory density equal or higher than 64 Kbytes. 6. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, UM0306, available from the STMicroelectronics website: www.st.com. 7. For the LQFP48 and LQFP64 packages, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins.
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Memory mapping
STM32F103xx
4
Memory mapping
The memory map is shown in Figure 6. Figure 6. Memory map
APB memory space
0xFFFF FFFF
reserved
0xE010 0000
reserved
0x6000 0000
reserved
0x4002 3400
4 Kbits 1 Kbit 3 Kbits 1 Kbit 3 Kbits 1 Kbit 3 Kbits 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 2 Kbits 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 35 Kbits 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 2 Kbits 1 Kbit 1 Kbit 2 Kbits 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 7 Kbits 1 Kbit 1 Kbit 1 Kbit
reserved
0x4002 3000
0xFFFF FFFF 0xFFFF F000
reserved
0x4002 2400
Flash Interface
0x4002 2000
7
0xE010 0000 0xE000 0000 Cortex-M3 Internal Peripherals
reserved
0x4002 1400 0x4002 1000 0x4002 0400
RCC reserved DMA
0x4002 0000
6
0xC000 0000
reserved
0x4001 3C00 0x4001 3800 0x4001 3400 0x4001 3000
USART1 reserved SPI1 TIM1
5
0xA000 0000
0x4001 2C00
ADC2
0x4001 2800
ADC1
0x4001 2400
reserved
0x4001 1C00
4
0x8000 0000
Port E
0x1FFF FFFF
0x4001 1800
reserved
0x1FFF F9FF OPTION BYTES 0x1FFF F800
Port D
0x4001 1400
Port C
0x4001 1000
Port B
0x4001 0C00
Port A
0x4001 0800
3
0x1FFF F000 0x6000 0000
EXTI
SYSTEM MEM ORY
0x4001 0400
AFIO
0x4001 0000
reserved
0x4000 7400
PWR BKP
2
reserved
0x4000 0000 PERIPHERALS
0x4000 7000 0x4000 6C00
reserved
0x4000 6800 0x4000 6400 0x4000 6000
bxCAN
shared 512 byte USB/CAN SRAM
USB Registers
1
0x2000 0000 SRAM 0x0801 FFFF
0x4000 5C00
I2C2
0x4000 5800
I2C1
0x4000 5400
reserved
0x4000 4C00
0
0x0000 0000 CODE 0x0800 0000
USART3
FLASH
0x4000 4800
USART2
0x4000 4400
reserved
0x4000 3C00
SPI2
0x4000 3800
reserved
0x4000 3400
IWDG
0x4000 3000
Reserved
WWDG
0x4000 2C00
RTC
0x4000 2800
reserved
0x4000 0C00
TIM4
0x4000 0800 0x4000 0400 0x4000 0000
TIM3 TIM2
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Electrical characteristics
5
5.1
Electrical characteristics
Test conditions
Unless otherwise specified, all voltages are referred to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25C and TA=TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 2 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8.
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Figure 7.
Pin loading conditions
Figure 8.
Pin input voltage
STM32F103xx pin C = 50 pF
VIN
STM32F103xx pin
ai14141
ai14142
5.1.6
Power supply scheme
Figure 9. Power supply scheme
VBAT
3.3 V
Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers)
1.8-3.6 V
Po wer swi tch
OUT
Level shifter
GP I/Os
IN
IO Logic Kernel logic (CPU, Digital & Memories)
VDD
VDD 1/2/3/4/5 VSS
Regulator
5 x 100 nF + 1 x 10 F
VDD VREF
1/2/3/4/5
3.3V
VDDA VREF+ VREFVSSA
ai14125
10 nF + 1 F
10 nF + 1 F
ADC
Analog: RCs, PLL, ...
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Electrical characteristics
5.1.7
Current consumption measurement
Figure 10. Current consumption measurement scheme
IDD_VBAT VBAT
IDD VDD
VDDA
ai14126
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Electrical characteristics
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5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 4: Voltage characteristics, Table 5: Current characteristics, and Table 6: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 4.
Symbol VDD-VSS VIN |VDDx| |VSSX - VSS| VESD(HBM)
Voltage characteristics
Ratings External 3.3 V supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min -0.3 VSS -0.3 VSS - 0.3 50 50 Max 4.0 +5.5 VDD+0.3 50 mV 50 see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) V Unit
1. All 3.3 V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V supply. 2. IINJ(PIN) must never be exceeded (see Table 5: Current characteristics). This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN < VSS.
Table 5.
Symbol IVDD IVSS IIO
Current characteristics
Ratings Total current into VDD power lines (source)(1) Total current out of VSS ground lines (sink)(1) Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRST pin Max. 150 150 25 -25 5 5 5 pins)(4) 25 mA Unit
IINJ(PIN) (2)(3) IINJ(PIN)
(2)
Injected current on HSE OSC_IN and LSE OSC_IN pins Injected current on any other pin(4) Total injected current (sum of all I/O and control
1. All 3.3 V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 3.3 V supply. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. 3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC characteristics. 4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
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STM32F103xx Table 6. Thermal characteristics
Ratings Storage temperature range
Electrical characteristics
Symbol TSTG TJ
Value -65 to +150
Unit C
Maximum junction temperature (see Thermal characteristics)
5.3
5.3.1
Operating conditions
General operating conditions
Table 7.
Symbol fHCLK fPCLK1 fPCLK2 VDD VBAT TA
General operating conditions
Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Backup operating voltage Ambient temperature range Conditions Min 0 0 0 2 1.8 - 40 Max 72 36 72 3.6 3.6 105 V V C MHz Unit
5.3.2
Operating conditions at power-up / power-down
The parameters given in Table 8 are derived from tests performed under the ambient temperature condition summarized in Table 7. Table 8.
Symbol tVDD
Operating conditions at power-up / power-down
Parameter VDD rise/fall time rate Conditions Min Typ Max Unit 20 20 s/V ms/V
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5.3.3
Embedded reset and power control block characteristics
The parameters given in Table 9 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 9.
Symbol
Embedded reset and power control block characteristics
Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Min Typ Max 2.1 2 2.18 2.26 2.08 2.16 Unit V V V V V V V V V V V V V V V V mV V V mV 4.5 mS
2.19 2.28 2.37 2.09 2.18 2.27 2.28 2.38 2.48 2.18 2.28 2.38 2.38 2.48 2.58 2.28 2.38 2.48 2.47 2.58 2.69 2.37 2.48 2.59 2.57 2.68 2.79 2.47 2.58 2.69 2.66 2.78 2.56 2.68 2.76 2.88 2.66 2.78 100 2.9 2.8 3 2.9
VPVD
Programmable voltage detector level selection
PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge)
VPVDhyst VPOR/PDR VPDRhyst
PVD hysteresis Power on/power down reset threshold PDR hysteresis 1 Falling edge Rising edge 1.8
1.88 1.96 2.0
1.84 1.92 40 2.5
TRSTTEMPO Reset temporization
5.3.4
Embedded reference voltage
The parameters given in Table 10 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 10.
Symbol VREFINT
Embedded internal reference voltage
Parameter Internal reference voltage Conditions - 45C < TA < +105C - 45C < TA < +85C Min 1.16 1.16 Typ 1.20 1.20 Max 1.26 1.24 Unit V V
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Electrical characteristics
5.3.5
Supply current characteristics
The current consumption is measured as described in Figure 10: Current consumption measurement scheme.
Maximum current consumption
The MCU is placed under the following conditions:

All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if it is explicitly mentioned The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)
The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 11.
Symbol
Maximum current consumption in Run and Sleep modes(1)
Max(3) Parameter Conditions FHCLK Typ(2) TA = 85 C TBD TBD TBD TBD TA= 105 C TBD TBD TBD TBD Unit
External clock with PLL, code running from Flash, all peripherals enabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK External clock, PLL stopped, code running from Flash, all peripherals enabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK External clock with PLL, code running from RAM, all peripherals enabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK External clock, PLL stopped, code running from RAM, all peripherals enabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK External clock with PLL, code running from RAM or Flash, all peripherals enabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK External clock, PLL stopped, code running from RAM or Flash, all peripherals enabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK
72 MHz 48 MHz 36 MHz 24 MHz
36 30 22 21
8 MHz
10
TBD
TBD mA
Supply current in Run mode
72 MHz 48 MHz 36 MHz 24 MHz
32 22 13 11
45 31 18 15
47 33 20 17
IDD
8 MHz
4.5
TBD
TBD
72 MHz 48 MHz 36 MHz 24 MHz
22 14 13 10
35 23 22 17
37 25 24 19 mA
Supply current in Sleep mode
8 MHz
3.5
TBD
TBD
1. TBD stands for to be determined. 2. Typical values are measured at TA = 25 C, and VDD = 3.3 V 3. Data based on characterization results, tested in production at VDmax, fHCLK max. TAmax, and code executed from RAM.
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Electrical characteristics Table 12.
Symbol
STM32F103xx
Maximum current consumption in Stop and Standby modes(1)
Typ(2) Parameter Conditions VDD/ VBAT VDD/VBAT = 2.4 V = 3.3 V Max(3) TA = 85 C TA = 105 C Unit
Supply current in Stop mode IDD
Regulator in Run mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Regulator in Low Power mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog OFF, lowspeed oscillator and RTC OFF
TBD
24
TBD
TBD
TBD(4)
14(4)
TBD(4) TBD(4)
A
Supply current in Standby mode(5) IDD_VBAT
TBD(4)
2(4)
TBD(4) TBD(4)
Backup domain Low-speed oscillator and RTC ON supply current
1(4)
1.4(4)
TBD(4) TBD(4)
1. TBD stands for to be determined. 2. Typical values are measured at TA = 25 C, VDD = 3.3 V, unless otherwise specified. 3. Data based on characterization results, tested in production at VDD max, fHCLK max. and TA max (for other temperature. 4. Values expected for next silicon revision. 5. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when VDD is present the Backup Domain is powered by VDD supply).
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Electrical characteristics
Typical current consumption
The MCU is placed under the following conditions:

All I/O pins are in input mode with a static value at VDD or VSS (no load). All peripherals are disabled except if it is explicitly mentioned. The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHZ and 2 wait states above). Ambient temperature and VDD supply voltage conditions summarized in Table 7. Typical current consumption in Run and Sleep modes(1)
Parameter Conditions fHCLK 72 MHz Oscillator running at 8 MHz with PLL, code running from Flash, all peripheral disabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2=fHCLK 48 MHz 36 MHz 24 MHz 16 MHz 8 MHz Running on HSI clock, code running from Flash, all peripheral disabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2=fHCLK. AHB pre-scaler used to reduce the frequency 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 8 MHz Running on HSI clock, code running from RAM, all peripheral disabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2=fHCLK. AHB pre-scaler used to reduce the frequency 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 72 MHz Oscillator running at 8MHz with PLL, code running from Flash, all peripheral disabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2=fHCLK Supply current in Sleep mode Running on HSI clock, code running from Flash, all peripheral disabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2=fHCLK. AHB pre-scaler used to reduce the frequency 48 MHz 36 MHz 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz Typ(2) 21 18 TBD 13 TBD 7.8 7 6.3 mA 6.2 6.1 5.95 2.3 1.6 1.2 mA 1 0.88 0.82 6 mA TBD TBD TBD 1 TBD TBD TBD TBD TBD mA mA Unit
Table 13.
Symbol
Supply current in Run mode
IDD
1. TBD stands for to be determined. 2. Typical values are measures at TA = 25 C, VDD = 3.3 V.
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Electrical characteristics Table 14.
Symbol
STM32F103xx
Typical current consumption in Stop and Standby modes(1)
Parameter Conditions Regulator in Run mode, Low-speed and high-speed internal RC oscillators OFF High-speed oscillator OFF (no independent watchdog) Regulator in Low Power mode, Low-speed and high-speed internal RC oscillators OFF, High-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog OFF Supply current in Standby mode(4) Low-speed internal RC oscillator and independent watchdog ON Low-speed internal RC oscillator ON, independent watchdog OFF Low-speed oscillator and RTC ON VDD 3.3 V 2.4 V 3.3 V 2.4 V 3.3 V 2.4 V 3.3 V 2.4 V 3.3 V 2.4 V 3.3 V Typ(2) 24 TBD 14(3) TBD(3) 2(3) TBD(3) 3.1(3) TBD(3) 2.9(3) TBD(3) 1.4(3) 1(3) 0.5(3) TBD(3) A A A Unit
Supply current in Stop mode
IDD
IDD_VBAT
Backup domain supply current Low-speed oscillator OFF, RTC ON
2.4 V 3.3 V 2.4 V
1. TBD stands for to be determined. 2. Typical values are measures at TA = 25 C, VDD = 3.3 V. 3. Values expected for next silicon revision. 4. To obtain Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby.
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Electrical characteristics
5.3.6
External clock source characteristics
High-speed external user clock
The characteristics given in Table 15 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 7. Table 15.
Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) IL
High-speed external (HSE) user clock characteristics
Parameter User external clock source frequency(1) OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN high or low time(1) OSC_IN rise or fall time(1) VSS VIN VDD 0.7VDD VSS 16 ns 5 1 A Conditions Min Typ 8 Max 25 VDD V 0.3VDD Unit MHz
OSC_IN Input leakage current
1. Value based on design simulation and/or technology characteristics. It is not tested in production.
Low-speed external user clock
The characteristics given in Table 16 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 7. Table 16.
Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) IL
Low-speed external user clock characteristics
Parameter User External clock source frequency(1) OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) OSC32_IN Input leakage current VSS VIN VDD 0.7VDD VSS 450 ns 5 1 A Conditions Min Typ 32.768 Max 1000 VDD V 0.3VDD Unit kHz
1. Value based on design simulation and/or technology characteristics. It is not tested in production.
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Electrical characteristics Figure 11. High-speed external clock source AC timing diagram
STM32F103xx
VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t
EXTER NAL CLOCK SOURC E
fHSE_ext OSC _IN
IL STM32F103xx ai14143
Figure 12. Low-speed external clock source AC timing diagram
VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t
EXTER NAL CLOCK SOURC E
fLSE_ext
OSC32_IN
IL STM32F103xx ai14144b
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Electrical characteristics
High-speed external clock
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 17. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 17.
Symbol fOSC_IN RF CL1 CL2(2) i2 gm
HSE 4-16 MHz oscillator characteristics(1)
Parameter Oscillator frequency Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) HSE driving current Oscillator Transconductance RS = 30 VDD= 3.3 V VIN=VSS with 30 pF load Startup VSS is stabilized 25 2 Conditions Min 4 Typ 8 200 30 Max 16 Unit MHz k pF
1
mA mA/V ms
tSU(HSE)(4) startup time
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included when sizing CL1 and CL2 (10 pF can be used as a rough estimate of the combined pin and board capacitance). 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
Figure 13. Typical application with a 8-MHz crystal
Resonator with integrated capacitors CL1
OSC_IN 8 MH z resonator REXT(1) OSC_OU T RF Bias controlled gain STM32F103xx fHSE
CL2
ai14145
1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.
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Electrical characteristics
STM32F103xx
Low-speed external clock
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 18. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 18.
Symbol RF CL1 CL2 I2 gm tSU(LSE)(2)
LSE oscillator characteristics (fLSE = 32.768 kHz)
Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(1) LSE driving current Oscillator Transconductance startup time VSS is stabilized RS = 30 k VDD = 3.3 V VIN = VSS 5 3 Conditions Min Typ 5 15 Max Unit M pF
1.4
A A/V s
1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
Figure 14. Typical application with a 32.768 kHz crystal
Resonator with integrated capacitors CL1
OSC32_IN 32.768 kH z resonator CL2 RF OSC32_OU T Bias controlled gain STM32F103xx fLSE
ai14146
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Electrical characteristics
5.3.7
Internal clock source characteristics
The parameters given in Table 19 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7.
High-speed internal (HSI) RC oscillator
Table 19.
Symbol fHSI
HSI oscillator characteristics(1)(2)
Parameter Frequency TA = -40 to 105 C at TA = 25C TBD TBD 1 80 Conditions Min Typ 8 3 1 TBD TBD 2 100 Max(3) Unit MHz % % s A
ACCHSI Accuracy of HSI oscillator tsu(HSI) IDD(HSI) HSI oscillator start up time HSI oscillator power consumption
1. VDD = 3.3 V, TA = - to 105 C unless otherwise specified. 40 2. TBD stands for to be determined. 3. Values based on device characterization, not tested in production.
LSI Low Speed Internal RC Oscillator
Table 20.
Symbol fLSI tsu(LSI) IDD(LSI)
LSI oscillator characteristics (1)
Parameter Frequency LSI oscillator start up time LSI oscillator power consumption 0.65 Conditions Min 30 Typ Max(2) 60 85 1.2 Unit kHz s A
1. VDD = 3 V, TA = - to 105 C unless otherwise specified. 40 2. Value based on device characterization, not tested in production.
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Wakeup time from low power mode
The wakeup times given in Table 21 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:

Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 21.
Symbol
Low-power mode wakeup timings(1)
Parameter Conditions Wakeup on HSI RC clock HSI RC wakeup time = 2 s HSI RC wakeup time = 2 s, Regulator wakeup from LP mode time = 5 s HSI RC wakeup time = 2 s, Regulator wakeup from power down time = 38 s Typ 0.75 4 Max TBD TBD s 7 TBD Unit s
tWUSLEEP(2) Wakeup from Sleep mode Wakeup from Stop mode (regulator in run mode) tWUSTOP(2) Wakeup from Stop mode (regulator in low power mode)
tWUSTDBY(3) Wakeup from Standby mode
1. TBD stands for to be determined.
40
TBD
s
2. The wakeup time from Sleep and Stop mode are measured from the wakeup event to the point in which the user application code reads the first instruction. 3. The wakeup time from Standby mode is measured from the wakeup event to the point in which the device exits from reset.
5.3.8
PLL characteristics
The parameters given in Table 22 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 22.
Symbol
PLL characteristics(1)
Value Parameter PLL input clock Test Conditions Min Typ 8.0 40 16 When PLL operates (locked) 32 60 72 144 200 VDD is stable TBD TBD Max(2) Unit MHz % MHz MHz s %
fPLL_IN fPLL_OUT fVCO tLOCK tJITTER
PLL input clock duty cycle PLL multiplier output clock VCO frequency range PLL lock time Cycle to cycle jitter (+/-3 peak to peak)
1. TBD stands for to be determined. 2. Data based on device characterization, not tested in production.
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STM32F103xx
Electrical characteristics
5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = - to 105 C unless otherwise specified. 40 Table 23.
Symbol tprog tERASE tME
Flash memory characteristics
Parameter Word programming time Page (1kB) erase time Mass erase time Conditions TA = - to +105 C 40 TA = - to +105 C 40 TA = - to +105 C 40 Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V Min 20 20 20 Typ Max(1) 40 40 40 Unit s ms ms
20
mA
IDD
Supply current
Write / Erase modes fHCLK = 72 MHz, VDD = 3.3 V Power-down mode / HALT, VDD = 3.0 to 3.6 V
5
mA
50
A
1. Values based on characterization and not tested in production.
Table 24.
Symbol NEND tRET
Flash memory endurance and data retention
Value Parameter Endurance Data retention TA = 85 C Conditions Min(1) 1 30 Unit Typ 10 Max kcycles Years
1. Values based on characterization not tested in production.
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Electrical characteristics
STM32F103xx
5.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in Table 25. They are based on the EMS levels and classes defined in application note AN1709. Table 25.
Symbol
EMS characteristics(1)
Parameter Conditions Level/ Class TBD
VFESD
VDD = 3.3 V, TA = +25 C, Voltage limits to be applied on any I/O pin to fHCLK=48 MHz induce a functional disturbance conforms to IEC 1000-4-2 Fast transient voltage burst limits to be VDD = 3.3 V, TA = +25 C, applied through 100pF on VDD and VSS pins fHCLK = 48 MHz to induce a functional disturbance conforms to IEC 1000-4-4
VEFTB
4A
1. TBD stands for to be determined.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:

Corrupted program counter Unexpected reset Critical Data corruption (control registers...)
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STM32F103xx Prequalification trials
Electrical characteristics
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J 1752/3 standard which specifies the test board and the pin loading. Table 26.
Symbol
EMI characteristics
Parameter Conditions Monitored Frequency Band Max vs. [fHSE/fHCLK] Unit 8/48 MHz 8/72 MHz 12 22 23 4 12 19 29 4 dBV
SEMI
Peak level
0.1 to 30 MHz VDD = 3.3 V, TA = 2 5 C, 30 to 130 MHz LQFP100 package compliant with SAE J 130 MHz to 1GHz 1752/3 SAE EMI Level
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Electrical characteristics
STM32F103xx
5.3.11
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size is either 3 parts (cumulative mode) or 3 parts x (n + 1) supply pins (non-cumulative mode). The human body model (HBM) can be simulated. The tests are compliant with JESD22A114A standard. For more details, refer to the application note AN1181. Table 27.
Symbol VESD(HBM) VESD(CDM)
ESD absolute maximum ratings(1)
Ratings Electrostatic discharge voltage (human body model) Electrostatic discharge voltage (charge device model) Conditions Maximum value(2) 2000 TA = +25 C TBD V Unit
1. TBD stands for to be determined. 2. Values based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up performance:

A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 28.
Symbol LU
Electrical sensitivities
Parameter Static latch-up class TA = +105 C Conditions Class II level A
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STM32F103xx
Electrical characteristics
5.3.12
I/O port pin characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 29 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. All unused pins must be held at a fixed voltage, by using the I/O output mode, an external pull-up or pull-down resistor (see Figure 15). Table 29.
Symbol VIL VIH VIL VIH
I/O static characteristics(1)
Parameter Input low level voltage(2) IO TC input high level voltage(2) IO FT high level voltage(2) Input low level voltage(2) CMOS ports 0.65 VDD 200 5% VDD(4) VSS VIN VDD Standard I/Os VIN= 5 V 5 V tolerant I/Os Weak pull-up equivalent resistor(6) Weak pull-down equivalent resistor(6) I/O pin capacitance VIN = VSS VIN = VDD 30 30 40 40 5 1 A 3 50 50 k k pF TTL ports Conditions Min -0.5 2 2 -0.5 Typ Max 0.8 V VDD+0.5 5.5V 0.35 VDD VDD+0.5 mV mV V Unit
Input high level voltage(2) IO TC Schmitt trigger voltage hysteresis(3)
Vhys
IO TC Schmitt trigger voltage hysteresis(3)
Ilkg
Input leakage current
(5)
RPU RPD CIO
40 1. VDD = 3.3 V, TA = - to 105 C unless otherwise specified. 2. Values based on characterization results, and not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. With a minimum of 100 mV. 5. Leakage could be higher than max. if negative current is injected on adjacent pins. 6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order).
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Electrical characteristics Figure 15. Unused I/O pin connection
VDD 1 0 k
STM32F103xx
STM32F103xx
UNU SED I/O PORT
STM32F103xx
UNU SED I/O PORT 1 0 k ai14147b
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2:
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 5). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 5).
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STM32F103xx
Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 30 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 30.
Symbol VOL(1) VOH(2) VOL (1) VOH (2) VOL(1) VOH(2) VOL (1) VOH (2)
Output voltage characteristics
Parameter Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 4 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 4 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 4 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 4 pins are sourced at same time Conditions TTL port IIO = +8 mA 2.7 V < VDD < 3.6 V CMOS port IIO =+ 8mA 2.7 V < VDD < 3.6 V Min Max 0.4 V VDD-0.4 0.4 V 2.4 1.3 V VDD-1.3 0.4 V VDD-0.4 Unit
IIO = +20 mA 2.7 V < VDD < 3.6 V
IIO = +6 mA 2 V < VDD < 2.7 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 5 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 5 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
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Electrical characteristics
STM32F103xx
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 16 and Table 31, respectively. Unless otherwise specified, the parameters given in Table 31 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 31.
I/O mode(1)
I/O AC characteristics(1)
Symbol Parameter Conditions CL = 50 pF, VDD = 2 V to 3.6 V Min Max Unit 2 125 CL = 50 pF, VDD = 2 V to 3.6 V 125 CL = 50 pF, VDD = 2 V to 3.6 V 10 25 CL = 50 pF, VDD = 2 V to 3.6 V 25 CL = 30 pF, VDD = 2.7 V to 3.6 V Fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V Output high to low level fall CL = 50 pF, VDD = 2.7 V to 3.6 V time(3) CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V tr(IO)out Output low to high level rise time(3) Pulse width of external signals detected by the EXTI controller CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V 50 30 20 5 8 12 ns 5 8 12 10 ns MHz MHz MHz ns MHz ns MHz
fmax(IO)out Maximum frequency(2) 10 tf(IO)out tr(IO)out Output high to low level fall time(3) Output low to high level rise time(3)
fmax(IO)out Maximum frequency(2) 01 tf(IO)out tr(IO)out Output high to low level fall time(3) Output low to high level rise time(3)
11
tf(IO)out
-
tEXTIpw
1. Refer to the Reference user manual UM0306 for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 16. 3. Values based on design simulation and validated on silicon, not tested in production.
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STM32F103xx Figure 16. I/O AC characteristics definition
Electrical characteristics
90% 50% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out
10% 50% 90% tr(I O)out T
Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF
ai14131
5.3.13
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 29). Unless otherwise specified, the parameters given in Table 32 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 32.
Symbol VIL(NRST) VIH(NRST) Vhys(NRST) RPU VF(NRST) VNF(NRST)
NRST pin characteristics(1)
Parameter NRST Input low level voltage NRST Input high level voltage NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor(2) NRST Input filtered pulse
(3)
Conditions
Min -0.5 2
Typ
Max 0.8
Unit V
VDD+0.5 200
VIN = VSS
30
40
50 100
k ns s
NRST Input not filtered pulse(3)
300
1. TBD stands for to be determined. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 3. Values guaranteed by design, not tested in production.
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Electrical characteristics Figure 17. Recommended NRST pin protection
STM32F103xx
External reset circuit NRST
VDD RPU FILTER 0.1 F Internal Reset
STM32F101xx
ai14132b
2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 32. Otherwise the reset will not be taken into account by the device.
5.3.14
TIM timer characteristics
Unless otherwise specified, the parameters given in Table 33 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 7. Refer to Section 5.3.12: I/O port pin characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 33.
Symbol tres(TIM)
TIMx(1) characteristics
Parameter Timer resolution time fTIMxCLK = 72 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 72 MHz Timer resolution 16-bit counter clock period 1 when internal clock is fTIMxCLK = 72 MHz 0.0139 selected 13.9 0 0 fTIMxCLK/2 36 16 65536 910 65536 x 65536 Conditions Min 1 Max Unit tTIMxCLK ns MHz MHz bit tTIMxCLK s tTIMxCLK s
fEXT ResTIM tCOUNTER
tMAX_COUNT Maximum possible count
fTIMxCLK = 72 MHz
59.6
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
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STM32F103xx
Electrical characteristics
5.3.15
Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 7. The STM32F103xx performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. In addition, there is a protection diode between the I/O pin and VDD. As a consequence, when multiple master devices are connected to the I2C bus, it is not possible to power off the STM32F103xx while another I2C master node remains powered on. Otherwise, the STM32F103xx would be powered by the protection diode. The I2C characteristics are described in Table 34. Refer also to Section 5.3.12: I/O port pin characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 34.
Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb
I2C characteristics
Standard mode I2C(1) Parameter Min SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time Repeated Start condition setup time Stop condition setup time Stop to Start condition time (bus free) Capacitive load for each bus line 4.0 4.7 4.0 4.7 400 4.7 4.0 250 0(3) 1000 300 Max Min 1.3 s 0.6 100 0(4) 20 + 0.1Cb 20 + 0.1Cb 0.6 s 0.6 0.6 1.3 400 s s pF 900(3) 300 300 ns Max Fast mode I2C(1)(2) Unit
1. Values based on standard I2C protocol requirement, not tested in production. 2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 4 MHz to achieve the maximum fast mode I2C frequency. 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
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Electrical characteristics Figure 18. I2C bus AC waveforms and measurement circuit
VDD 4 .7 k I2C bus VDD 4 .7 k STM32F103xx SDA 100 SCL
STM32F103xx
100
S TART REPEATED S TART tsu(STA) SDA tf(SDA) th(STA) SCL tw(SCKH) S TART
tr(SDA) tw(SCKL)
tsu(SDA) th(SDA) S TOP
tsu(STA:STO)
tr(SCK)
tf(SCK)
tsu(STO)
ai14149b
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 35.
SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2)(3)
I2C_CCR value fSCL (kHz) RP = 4.7 k 400 300 200 100 50 20 TBD TBD TBD TBD TBD TBD
1. TBD = to be determined. 2. RP = External pull-up resistance, fSCL = I2C speed, 3. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed 2%. These variations depend on the accuracy of the external components used to design the application.
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STM32F103xx
Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 7. Refer to Section 5.3.12: I/O port pin characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 36.
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(2) th(NSS)(2)
(2)
SPI characteristics(1)
Parameter SPI clock frequency Slave mode SPI clock rise and fall time NSS setup time NSS hold time Capacitive load: C=50 pF Slave mode Slave mode Master mode, fPCLK= TBD, presc = TBD Master mode Data input setup time Slave mode Master mode TBD TBD TBD TBD(3) TBD(3) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD ns 0 0 TBD TBD 0 TBD TBD Conditions Master mode Min TBD Max TBD MHz Unit
SCK high and low tw(SCKH) tw(SCKL)(2) time tsu(MI) (2) tsu(SI)(2)
th(MI) (2) th(SI)(2)
Slave mode Data input hold time Master mode, fPCLK= TBD Slave mode, fPCLK= TBD
ta(SO)(2)(4) tdis(SO)(2)(5)
Data output access time Data output disable time
Slave mode Slave mode, fPCLK= TBD Slave mode Slave mode (after enable edge) fPCLK= TBD Master mode (after enable edge) fPCLK= TBD
tv(SO) (2)(1) Data output valid time
tv(MO)
(2)(1)
Data output valid time
th(SO)(2) th(MO)(2) Data output hold time
Slave mode (after enable edge) Master mode (after enable edge)
1. TBD = to be determined. 2. Values based on design simulation and/or characterization results, and not tested in production. 3. Depends on fPCLK. For example, if fPCLK= 8MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns. 4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
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Electrical characteristics Figure 19. SPI timing diagram - slave mode and CPHA = 0
STM32F103xx
NSS input tSU(NSS) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tc(SCK) th(NSS)
tw(SCKH) tw(SCKL) tv(SO) MS B O UT tsu(SI) tr(SCK) tf(SCK) LSB OUT
ta(SO) MISO OUT P UT MOSI I NPUT
th(SO) BI T6 OUT
tdis(SO)
M SB IN th(SI)
B I T1 IN
LSB IN
ai14134
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Figure 20. SPI timing diagram - slave mode and CPHA = 11)
NSS input tSU(NSS) SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) th(NSS)
tw(SCKH) tw(SCKL) tr(SCK) tf(SCK)
ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN
tv(SO) MS B O UT th(SI)
th(SO) BI T6 OUT
tdis(SO) LSB OUT
B I T1 IN
LSB IN
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STM32F103xx Figure 21. SPI timing diagram - master mode
High NSS input tc(SCK) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1
Electrical characteristics
SCK Input
CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO)
ai14136
tr(SCK) tf(SCK) BI T6 IN LSB IN
LSB OUT
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
USB characteristics
The USB interface is USB-IF certified (Full Speed). Table 37.
Symbol Input levels VDI VCM VSE Differential input sensitivity Differential common mode range Single ended receiver threshold I(USBDP, USBDM) Includes VDI range 0.2 0.8 1.3 2.5 2.0 V
USB DC electrical characteristics
Parameter Conditions Min.(1) Max.(1) Unit
Output levels VOL VOH Static output level low Static output level high RL of 1.5 k to 3.6 V(2) RL of 15 k to VSS(2) 2.8 0.3 V 3.6
1. All the voltages are measured from the local ground potential. 2. RL is the load connected on the USB drivers
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Electrical characteristics Figure 22. USB timings: definition of data signal rise and fall time
STM32F103xx
Crossover points Differen tial Data L ines V CRS VS S tf tr
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Table 38. Symbol
USB: Full speed electrical characteristics Parameter Conditions Min Max Unit
Driver characteristics tr tf trfm VCRS Rise time(1) Fall Time(1) Rise/ fall time matching Output signal crossover voltage CL = 50 pF CL = 50 pF tr/tf 4 4 90 1.3 20 20 110 2.0 ns ns % V
1. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0).
5.3.16
CAN (controller area network) interface
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX).
5.3.17
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 39 are derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 7.
Note:
It is recommended to perform a calibration after each power-up. Table 39.
Symbol VDDA VREF+ fADC fS fTRIG VAIN
ADC characteristics(1)
Parameter ADC power supply Positive reference voltage ADC clock frequency Sampling rate External trigger frequency Conversion voltage range(2) TBD fADC = 14 MHz VSSA Conditions Min 2.4V 2.0 0.6 0.05 Typ Max 3.6V VDDA 14 1 823 17 VDDA Unit V V MHz MHz kHz 1/fADC V
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STM32F103xx Table 39.
Symbol RAIN CAIN Ilkg RADC CADC tCAL
Electrical characteristics ADC characteristics(1) (continued)
Parameter External input impedance External capacitor on analog input Negative input leakage current VIN < VSS, | IIN | < 400 A on analog pins on adjacent analog pin Sampling switch resistance Internal sample and hold capacitor 5.9 Calibration time fADC = 14MHz 83 0.214 Injection conversion latency Sampling time Power-up time fADC = 14 MHz fADC = 14 MHz 0.107 0 1 0 3 17.1 1 18 TBD(2)(3) pF 5 6 1 5 A k pF s 1/fADC s 1/fADC s s s 1/fADC Conditions Min Typ Max Unit k
tlat tS tSTAB
tCONV
Total conversion time (including sampling time)
fADC = 14 MHz
14 (1.5 for sampling +12.5 for successive approximation)
1. TBD = to be determined. 2. Depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and reduced to allow the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies 14 MHz. 3. During the sample time the input capacitance CAIN (5 max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming.
Table 40.
Symbol |ET| |EO| |EG| |ED| |EL|
ADC accuracy (fPCLK2 = 14 MHz, fADC = 14 MHz, RAIN <10 k VDDA = , 3.3 V)(1)
Parameter Total unadjusted error(2) Offset Gain error(2) Conditions Typ 3 1 2 3 2 Max TBD TBD TBD TBD TBD LSB Unit
Error(2)
Differential linearity error(2) Integral linearity error(2)
1. TBD = to be determined. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not affect the ADC accuracy.
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Electrical characteristics Figure 23. ADC accuracy characteristics
EG 1023 1022 1021 1LSB IDEAL V -V DDA SSA = ----------------------------------------
STM32F103xx
(1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line
1024
(2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1)
ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
5
6
7
1021 1022 1023 1024 VDDA
ai14395
Figure 24. Typical connection diagram using the ADC
VDD VT 0.6V RAIN AINx VT 0.6V RADC 12-bit A/D conversion CADC STM32F103xx
VAIN
CAIN(1)
IL1mA
ai14150
1. Refer to Table 39 for the values of RADC and CADC. 2. CPARASITIC must be added to CAIN. It represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
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STM32F103xx
Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 25 or Figure 26, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 25. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F103xx
VREF+ (see note 1)
1 F // 10 nF
VDDA
1 F // 10 nF VSSA /VREF+ (see note 1)
ai14388
1. VREF+ and VREF- inputs are available only on 100-pin packages.
Figure 26. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F103xx
VREF+/VDDA (See note 1)
1 F // 10 nF
VREF-/VSSA (See note 1)
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1. VREF+ and VREF- inputs are available only on 100-pin packages.
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Electrical characteristics
STM32F103xx
5.3.18
Temperature sensor characteristics
Table 41.
Symbol
TS characteristics
Parameter VSENSE linearity with temperature Average slope Voltage at 25 C Startup time 4 Conditions Min Typ Max Unit C mV/C V 10 s
TL
Avg_Slope V25 tSTART
1.5
4.478 1.4
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STM32F103xx
Package characteristics
6
Package characteristics
Figure 27. LFBGA100 - low profile fine pitch ball grid array package outline
C Seating plane ddd C
A2 A4 A3 B e D D1 F
A1
A
A
K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10
F
E1
E
e
A1 corner index area (see note 5)
b (100 eee
balls)
MCAB fff M C
ai14396
Bottom view
Table 42.
Dim.
LFBGA100 - low profile fine pitch ball grid array package mechanical data
mm Min Typ Max 1.700 0.270 1.085 0.30 0.80 0.45 9.85 0.50 10.00 7.20 9.85 10.00 7.20 0.80 1.40 0.12 0.15 0.08 100 10.15 0.388 0.55 10.15 0.018 0.388 0.020 0.394 0.283 0.394 0.283 0.031 0.055 0.005 0.006 0.003 0.40 0.011 0.043 0.012 0.031 0.022 0.40 Min inches Typ Max 0.067
A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff N (number of balls)
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Package characteristics Figure 28. Recommended PCB design rules (0.80/0.75 mm pitch BGA)
STM32F103xx
Dpad
0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.37 mm aperture diameter - Non solder mask defined pads are recommended - 4 to 6 mils screen print
Dpad Dsm
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STM32F103xx
Package characteristics
Figure 29. LQFP100 - 100-pin low-profile quad flat package outline
D D1 A A2
A1
b
e E1 E
L1 L h
c
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Table 43.
Dim.
LQFP100 - 100-pin low-profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.17 0.09 16.00 14.00 16.00 14.00 0.50 0 0.45 3.5 0.60 1.00 Number of pins 7 0.75 0 0.018 1.40 0.22 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 0.630 0.551 0.630 0.551 0.020 3.5 0.024 0.039 7 0.030 0.055 0.009 Min inches Typ Max 0.063 0.006 0.057 0.011 0.008
A A1 A2 b C D D1 E E1 e L L1
N
100
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Package characteristics Figure 30. LQFP64 - 64 pin low-profile quad flat package outline
D D1 A1
STM32F103xx
A A2
b
E1
E e
c L1 L
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Table 44.
Dim.
LQFP64 - 64 pin low-profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 Number of pins 7 0.75 0 0.018 1.40 0.22 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 0.472 0.394 0.472 0.394 0.020 3.5 0.024 0.039 7 0.030 0.055 0.009 Min inches Typ Max 0.063 0.006 0.057 0.011 0.008
A A1 A2 b c D D1 E E1 e L L1
N
64
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STM32F103xx
Package characteristics
Figure 31. LQFP48 - 48 pin low-profile quad flat package outline
D D1 A1 b A A2
E1
E
e
L1 L
c
ai14399
Table 45.
Dim.
LQFP48 - 48 pin low-profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.17 0.09 9.00 7.00 9.00 7.00 0.50 0 0.45 3.5 0.60 1.00 Number of pins 7 0.75 0 0.018 1.40 0.22 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 0.354 0.276 0.354 0.276 0.020 3.5 0.024 0.039 7 0.030 0.055 0.009 Min inches(1) Typ Max 0.063 0.006 0.057 0.011 0.008
A A1 A2 b C D D1 E E1 e L L1
N
48
1. Values in inches are converted from mm and rounded to 3 decimal digits.
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Package characteristics
STM32F103xx
6.1
Thermal characteristics
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the following equation: TJ = TA + (PD x JA) Where:

(1)
TA is the Ambient Temperature in C, JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, PD is the sum of PINT and PI/O (PD = PINT + PI/O), PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power.
PI/O represents the Power Dissipation on Input and Output Pins; Most of the time for the application PI/O < PINT and can be neglected. On the other hand, PI/O may be significant if the device is configured to drive continuously external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273 C) Therefore (solving equations 1 and 2): K = PD x (TA + 273C) + JA x PD2 where: K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA. Table 46.
Symbol
(2)
(3)
Thermal characteristics
Parameter Thermal resistance junction-ambient LFBGA100 - 10 x 10 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch Thermal Resistance Junction-Ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch Thermal resistance junction-ambient LQFP48 - 7 x 7 mm / 0.5 mm pitch Value 41 46 C/W 45 55 Unit
JA
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STM32F103xx
Order codes
7
Order codes
Table 47. Order codes
Part number Flash program memory Kbytes STM32F103C6T6 STM32F103C8T6 STM32F103R6T6 STM32F103R8T6 STM32F103RBT6 STM32F103V8T6 STM32F103VBT6 STM32F103V8H6 STM32F103VBH6 32 64 32 64 128 64 128 64 128 SRAM memory Kbytes 10 LQFP48 20 10 20 20 20 LQFP100 20 20 LFBGA100 20 LQFP64 Package
7.1
Future family enhancements
Further developments of the STM32F103xx performance line will see an expansion of the current options. Larger packages will soon be available with up to 512KB Flash, 64KB SRAM and with extended features such as EMI support, SDIO, I2S, DAC and additional timers and USARTS.
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Revision history
STM32F103xx
8
Revision history
Table 48.
Date 01-jun-2007
Document revision history
Revision 1 Initial release. Flash memory size modified in Note 5, Note 4, Note 6, Note 7 and BGA100 pins added to Table 3: Pin definitions. Figure 5: STM32F103xx performance line BGA100 ballout added. THSE changed to TLSE in Figure 12: Low-speed external clock source AC timing diagram. VBAT ranged modified in Power supply schemes. tSU(LSE) changed to tSU(HSE) in Table 17: HSE 4-16 MHz oscillator characteristics. IDD(HSI) max value added to Table 19: HSI oscillator characteristics. Sample size modified and machine model removed in Electrostatic discharge (ESD). Number of parts modified and standard reference updated in Static latch-up. 25 C and 85 C conditions removed and class name modified in Table 28: Electrical sensitivities. RPU and RPD min and max values added to Table 29: I/O static characteristics. RPU min and max values added to Table 32: NRST pin characteristics. Figure 18: I2C bus AC waveforms and measurement circuit and Figure 17: Recommended NRST pin protection corrected. Notes removed below Table 7, Table 32, Table 37. IDD typical values changed in Table 11: Maximum current consumption in Run and Sleep modes. Table 33: TIMx characteristics modified. tSTAB, VREF+ value, tlat and fTRIG added to Table 39: ADC characteristics. In Table 24: Flash memory endurance and data retention, typical endurance and data retention for TA = 85 C added, data retention for TA = 25 C removed. VBG changed to VREFINT in Table 10: Embedded internal reference voltage. Document title changed. Controller area network (CAN) section modified. Figure 9: Power supply scheme modified. Features on page 1 list optimized. Small text changes. Changes
20-Jul-2007
2
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STM32F103xx
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